Verilog Hdl Synthesis: A Practical Primer

by Jayaram Bhasker

Book Overview

With this book, you can: - Start writing synthesizable Verilog models quickly. - See what constructs are supported for synthesis and how these map to hardware so that you can get the desired logic. -... This description may be from another edition of this product.

• Format: Paperback
• Language: English
• ISBN: 0965039153
• ISBN13: 9780965039154
• Release Date: January 1998
• Publisher: Star Galaxy Pub
• Length: 215 Pages
• Weight: 0.80 lbs.
• Dimensions: 6.5" x 9.0"

Customer Reviews

This is a very good (and short) book on Verilog synthesis

The author does a very good job of covering synthesizable Verilog. The numerous examples provide the reader with solid Verilog coding style guidelines. In addition, the author's discussion of blocking and non-blocking assignment statements for synthesizing combinational and sequential logic is very clear and concise. The only complaint I have about the book is its weak treatment of parameterizable design for synthesis. Despite the drawback, this is a very good reference and coding style guide for writing synthesizable Verilog.

A Synthesis Book...At Last

I write this review for two books: Verilog HDL Primer and Verilog HDL "SYNTEHSIS" Primer. Both books are primers, but serve the title very well. The books are straight to the point and do not "ramble" with grammar (ie. he tells you what it is you need to know and does not attempt to distract you). This is the book I use when I look for Verilog contructs for synthesis. The examples resemble closer to real world application including techniques in modeling digital systems. No comparison to the "other" Verilog text (Palnitkar). These two books complement one another. Another good verilog book is by Sternheim, but it is relatively expensive and hard to get.

Best Verilog Synthsis book

This is the best book about the Verilog Synthesis. The book is very practical, and I immediately applied many examples into my work....

Great Verilog info for Synthesis

This book is an excellant reference for anyone writing Verilog for synthesis. I found the examples useful and complete.

Excellent and Practical guide for today's RTL design

This book gives many examples to help immediate application for practical design. Synthesis is much more important than simulation, because that the major reason of rapid increase of HDL designers is the recent availability of synthesis tool. However, many published books spend little effort for synthesis. This book is the first book that intensively focuses the synthesis in the user's view; how to desribe design to generate intended circuit. No complicated talk on CAD technology. The discussion on blocking vs non-blocking assignments is also valuable for an advancved understanding on the semantic consistency between synthesis and simulation.This book is a really excellent and practical guide for today's RTL design.