Arnold: Verilog Dig Comp Des* _c

by Mark Arnold

Useful for introductory-level courses in Verilog Hardware Description Language, this book introduces the Verilog Hardware Description Language as a different way to explore concepts in digital and... This description may be from another edition of this product.

• Format: Paperback
• Language: English
• ISBN: 0136392539
• ISBN13: 9780136392538
• Release Date: January 1998
• Publisher: Prentice Hall
• Length: 592 Pages
• Weight: 2.45 lbs.
• Dimensions: 1.1" x 7.3" x 9.6"

Customer Reviews

Gets you off to a running start

I got this book as a quick tutorial on the Verilog language. After just a day or two with this book and a compiler to play with, I had the level of skill that I wanted. The Verilog language description is just one chapter in this book, though, and not even the longest one.This is lots more than just a language book. It also shows a higher level of design than most students see in their first few logic courses. The example developed in the book's later sections works up to a supersclar ARM processor core! This book is not about hooking up a few gates and latches. It actually starts to address problems of practical size and complexity. Big problems really are different from small ones, and I was very happy to see techniques for the larger systems.That said, beginning logic designers may find the book frustrating. It works at a high conceptual level and fast pace. The author assumes that the reader already has good command of the basics of boolean logic, synchronous design, and computer architecture. Initially, I just wanted a competent language description. I got that, plus some worthwhile design technique. Best of all, I did not have to sit through yet another lesson in the baby steps of logic design.

enlightening!

this book is an insightful and exciting introduction to hardwaredesign, especially to those like me with a software background.the author illuminates the difference between hardware andsoftware specification, and demonstrates how his "implicit"(RTL) approach works well for (synthesis of) pipelined CPU designs.the only deficit is that some of the free tools listed in theappendix are no longer available.

A good introductin to ASM and Implicit style Verilog

ASM and Verilog are cool stuff for digital designers, however implicit style Verilog is unlikely to be widely adopted. Sythesis tools do not support this style.