System-On-A-Chip Verification: Methodology and Techniques

by Peter Paterson, Leena Singh, Prakash Rashinkar

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical...

• Format: Paperback
• Language: English
• ISBN: 1475774680
• ISBN13: 9781475774689
• Release Date: April 2013
• Publisher: Springer
• Length: 372 Pages
• Weight: 1.22 lbs.
• Dimensions: 0.8" x 6.1" x 9.2"