Nano-CMOS Gate Dielectric Engineering

by Hei Wong

According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving...

• Format: Hardcover
• Language: English
• ISBN: 1439849595
• ISBN13: 9781439849590
• Release Date: November 2011
• Publisher: CRC Press
• Length: 248 Pages
• Weight: 1.19 lbs.
• Dimensions: 0.9" x 6.3" x 9.0"