Logic Synthesis and Verification Algorithms

by Gary D. Hachtel and Fabio Somenzi

Book Overview

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments...

• Format: Hardcover
• Language: English
• ISBN: 0792397460
• ISBN13: 9780792397465
• Release Date: June 1996
• Publisher: Springer
• Length: 564 Pages
• Weight: 2.80 lbs.
• Dimensions: 1.6" x 7.3" x 10.3"

Customer Reviews

exceptional...

This book is good. It covers all the fundamentals needed to learn two level and multi level logic synthesis and verification. It's a good stepping stone for those readers wanting to delve more into the IEEE publications area later on in their careers when implementing new algorithms for logic synthesis.

nachiketh potlapally

I had the oppurtunity to study this book in my graduate study. I think it is a well-written book, which has a substantial coverage of the field of logic synthesis and verification. I would highly recommend this book to advanced readers and those who are mathematically inclined. The expertise of the authors is reflected in the content of the book, and this can be fully appreciated by the readers having the qualifications mentioned above.