Logic Synthesis and Soc Prototyping: Rtl Design Using VHDL

by Vaibbhav Taraate

Emphasises SOC architecture and micro-architecture design with case studies

Consists of the practical scenarios and issues and helpful to graduate students and professionals

Covers SOC Design, implementation using VHDL, Synthesis and timing analysis

Covers key case studies in the generic form for processor, buses, interfaces, memory controllers, DSP and Video controllers

• Format: Hardcover
• Language: English
• ISBN: 9811513139
• ISBN13: 9789811513138
• Release Date: January 2020
• Publisher: Springer
• Length: 251 Pages