Hierarchical Modeling for VLSI Circuit Testing

by John P. Hayes and Debashish Bhattacharya

Book Overview

Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob- lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in...

• Format: Hardcover
• Language: English
• ISBN: 079239058X
• ISBN13: 9780792390589
• Release Date: December 1989
• Publisher: Springer
• Length: 160 Pages
• Weight: 0.94 lbs.
• Dimensions: 0.4" x 6.1" x 9.2"