Computer Architecture: A Quantitative Approach [With CDROM]

by Hennessy, David A. Patterson, John L. Hennessy

Book Overview

Computer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and... This description may be from another edition of this product.

• Format: Paperback
• Language: English
• ISBN: 0123704901
• ISBN13: 9780123704900
• Release Date: September 2006
• Publisher: Morgan Kaufmann Publishers
• Length: 704 Pages
• Weight: 2.66 lbs.
• Dimensions: 1.1" x 7.5" x 9.3"

Customer Reviews

Excellent deep-dive into processor architecture

This book isn't for the timid. It goes deep into several recent CPU designs and explains why the architectures turned out the way they did. There is decent coverage of RISC versus CISC ideas, and why CISC now dominates (hint: it is a combination of luck, marketing, and massive amounts of available transistors, plus new ways of instruction-level parallelism). It does not cover the absolute latest processors. But it doesn't have to. It will give you the background needed that when you go to the website that have technical details of a new architecture (e.g. Ars Technica), chances are good you will know the concepts they reference. Who shouldn't buy this: Programmer's in high level languages expecting to learn some black magic way to speed up your code. Even assembly language programmers have been mostly sidelined by the power of a modern CPU to optimize high-level languages.

The next edition of the definitive series; another must-have

Computer architecture has seen vast changes in the last 20 years, and fortunately, H & P somehow manage to do a new edition about every 5 years, often enough to stay current. When the First Edition appeared, it quickly became *the* standard textbook on the topic, to be replaced in that role by each successive edition. Computer architectures complexify over time, and so do books. The Third Edition was about 1100 pages long. The Fourth has been shrunk back to something more manageable by moving subsidiary details to a CD included with the book. This edition is well worth having, even if one already has the earlier ones. In particular, the additional material on multiprocessors is especially welcome, given that it has become much more difficult to speed up uniprocessors. Most people who work in or near computer systems architecture know these books, but I have often recommended them to others, such as technology journalists, venture capitalists, and financial analysts, i.e., people who are rarely computer archtiects, but need to understand computer technology and its trends. Many such have been surprised to find the book was useful to them. H & P write very clearly, and each chapter outlines its key concepts for a topic, then works down to detailed analyses, and then comes back up to summarize. hence, I've often recommended to people: 1) Read the first few sections of each chapter. 2) In each remaining section per chapter, read until the going gets heavy, then skip to the next section. In some cases, this will happen after reading the first paragraph, but don't worry, the writing will return to a higher level. 3) Read "Concluding Remarks" and any "Fallacies and Pitfalls" or Historical Perspectives" sections at the end of a chapter. Anyway, I expect this Edition will be just as indispensable as the earlier ones.

also has historical perspective

A massive and 2003 updated text. It gives comprehensive details of how to understand and design computer hardware. Naturally, a lot of effort is expended on the logic of the CPU. But memory hierarchy, storage systems (mostly disks) and interconnect issues are also heavily gone into. Along with alternative multiprocessor configurations. It is probably true to say that all the major ideas in the field are present in this text. With an emphasis on the student being able to make quantitative assessments of design. Buttressed by lengthy exercises in each chapter. Interestingly, the book also offers a bonus. The chapters end in historical sections. These give a perspective on the major events and persons for the chapters' topics. So often in computing, students have little appreciation of who made the key advances and why.

The milestone and its third edition

First, this is certainly not an introductory text on Computer Architectures. The authors assume that people reading it have already had an introductory class or some experience. Simply put, the book is not intended to explain how cache memory works, but to present a thourough quantitative analysis to show why and when one implementation works better than another, and what improvements have been devised recently to speed this or this other measurement.Of course, the best choice for this book would be to have it preceeded by "Computer Organization: the HW/SW interface" (aka CO-HSI), by the same authors, since it would help to better comprehend the MIPS64 and the low-level design behind it, since CO-HSI develop an older version of the MIPS itself.This is for sure one of the most informative books I've ever encountered both as a student and as a SW engineer. It contains an overwhelming quantity of data, tips, warnings, tecniques so that the over 1100 pages seem incredibly dense. And don't be fooled the book is "only so little": there are other seven online appendixes that can be downloaded, that will add up to more than 250 pages to the book.As experience teaches, however, quantity does not always mean quality. Yet, it seems this doesn't apply to this book, because the quality of its content is highly informative and interesting for those involved with true CA designs.Since the first chapter it's clear that target of the book is not a survery of CAs, but a guide through the bunch of considerations and problems a design of a new CA must cope with today. I mean today because much of the data collected and presented is binded to (and updated to) the current edition and its realease date. So covered CAs for this 3ed will feature IA-64 or Sony Playstation II among the others. Nonetheless, it would be misleading to think that next year the book will become useless. Most of the considerations the authors develop and present are quite long lasting (the usage patterns of ISAs, e.g., have incurred little change since the second edition, six years ago).This edition presents noticeable changes, even if there's no doubt the core is that of CA-AQA 2ed. To mention a few, the first chapter is of course almost totally new since it's the most time-bounded of the book. The elder chapter four (Advanced Pipelining and Instruction Level Parallellism) has been expanded into two chapters, one dealing with Hardware approaches and one with Software approaches (and both with hybrid ones). This goes into great benefit for the reader since it seems we never get enough details on modern CAs and their complexity otherwise.However, changes has been done even in the way of reductions, and that's especially true for the elder chapter three (Pipelining). It was a full 100 pages chapter, featuring an astonishing treatment of the topic, that has been fundamental in my class of CA II. In the 3ed edition, this chapter has been moved to a shorter appendix at the end, and I think this appen

PhD. In a box

This book is one of the few books out there that manages to have a huge page count but remain packed with the same fluedity and comprehension, and ciriculum, that makes you feel as though you wasted your money on graduate school, and could have just spent 80 some odd for this book. If you have ever been frustrated with the level of incompetance and stupidity in the reatail computer book market, where everone and their dogs sisters brother's uncle sallys, cosins sister is either a for dummies author, or some fool writing about thier experience with Windows, than this is the book for you, This book will take you to new levels of understanding of computers, the authors cover things like what Pipelining really is, and things like why MIPS is not a good mesure for performance, etc. At the end of each chapter the authors have a section called Fallicies and Pitfalls, which give you inside perspective from the Experts as to why some things are bad mesuremnts and or Engineering philospies, that exist today. Rest assured also that this book is not written by no name Professors. The first Author D. Patterson, along with Carlo Sequin coined the name RISC for there newly fashiond RISC chip, the second J. Hennesey invented the what he called the MIPS chip, both higly important chips to Companys like Sun and SGI and both authors have numorus awards for Engineering and Education and hail from highly acreddited universities, namely UC Berkly and Stanford. This book will not leave you waxing and waining for more, but rather fill you with the understanding and knowledge that are key to making a good engineer. Put simply, this book will not teach you the basics, this book will teach you the "advanced" and I really do mean the adVANced.