ASIC Design and Synthesis: Rtl Design Using Verilog

by Vaibbhav Taraate

Book Overview

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance...

• Format: Paperback
• Language: English
• ISBN: 9813346442
• ISBN13: 9789813346444
• Release Date: January 2022
• Publisher: Springer
• Length: 330 Pages
• Weight: 1.09 lbs.
• Dimensions: 0.7" x 6.1" x 9.2"