Advanced Hdl Synthesis and Soc Prototyping: Rtl Design Using Verilog

by Vaibbhav Taraate

Explains SOC architecture and micro-architecture design with case studies

Covers practical scenarios and issues, helpful to both students and professionals

Discusses systems design and testing scenarios using modern FPGAs

• Format: Hardcover
• Language: English
• ISBN: 981108775X
• ISBN13: 9789811087752
• Release Date: January 2019
• Publisher: Springer
• Length: 307 Pages
• Weight: 1.41 lbs.
• Dimensions: 0.8" x 6.1" x 9.2"